By Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund
Analog Circuit layout comprises the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and beneficial layout principles within the sector of analog circuit layout. every one half is gifted by means of six specialists in that box and state-of-the-art info is shared and overviewed. This ebook is quantity 18 during this winning sequence of Analog Circuit layout, supplying worthwhile info and ideal overviews of: clever info Converters: Chaired by means of Prof. Arthur van Roermund, Eindhoven college of expertise, Filters on Chip: Chaired by means of Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired through Prof. M. Steyaert, Catholic college Leuven, Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the academic insurance additionally makes it compatible to be used in a sophisticated layout.
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Extra resources for Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters
In the realization of , a 10mW auxiliary ADC is used to monitor the gain of the first residue amplifier, helping to cut its power in half. This overhead is justifiable in this high-performance ADC that dissipates a total power of 850 mW. In general, when applying this particular or a similar technique, the benefits must be carefully evaluated against the cost of the added calibration. An alternative to handling the low amplifier gain through calibration is to apply some form of double sampling to boost the effective gain of the amplifier.
A CMOS pipeline algorithmic A/D converter, in Proceedings of the IEEE Custom Integrated Circuits Conference, Rochester, Sept 1984, pp. 559–562 2. H. R. Gray, A pipelined 5-Msample/s 9-bit analog-to-digital converter. IEEE J. Solid-State Circuits 22(6), 954–961 (1987) 3. S. R. Gray, A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter. IEEE J. Solid-State Circuits 23(6), 1316–1323 (1988) 4. H. , A 10-b 20-Msample/s analog-to-digital converter. IEEE J. Solid-State Circuits 27(3), 351–358 (1992) 5.
E. Iroaga, B. Murmann, A 12-Bit 75-MS/s pipelined ADC using incomplete settling. IEEE J. Solid-State Circuits 42(4), 748–756 (2007) 69. S. , A 15b power-efficient pipeline A/D converter using non-slewing closedloop amplifiers, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2008, pp. 117–120 70. T. , Power dissipation bounds for high-speed Nyquist analog-to-digital converters. IEEE Trans. Circuits Syst. I 56(3), 509–518 (2009) Chapter 3 Low-Power Successive Approximation ADCS for Wireless Applications Jan Craninckx Abstract This chapter discusses the advancements made in SAR ADCs for wireless applications, which require accuracies in the range of 8–10 bit and a few 10’s of MHz sampling speed.
Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters by Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund