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Additional resources for ACM Transactions on Design Automation of Electronic Systems (January)
In a synthesis environment, where such templates are recognized for a given application during compilation, it is crucial to utilize these optimized modules during the actual synthesis of the datapath at the high-level synthesis stage. For mapping designs on such special architectures, there is a need for synthesis tools that are aware of the features of the underlying hardware resources. The customized cores certainly improve the application’s running time since they are superior in delay to their counterparts implemented with reconfigurable logic.
Several efficient heuristics have been proposed in the literature for these problem instances. Two of the most widely used approaches are list scheduling and force-directed scheduling. List scheduling maintains an ordered list of operations that can potentially be scheduled at a control step with no violation of data dependency. Considering one control step at a time, operations are selected from this ordered list one by one according to some priority function and scheduled at the control step under consideration.
The main goal here is to utilize the optimized blocks to improve the system performance. Such programmable devices are targeted for a class of applications, such as DSP [Xilinx, Inc. ] networking, or data communications [Lucent Technologies]. Embedded fixed blocks are tailored for the critical operations common to the application class. In essence, the flexible programmable logic is supported with the high-density, high-performance cores. ]. In the context of reconfigurable systems, there have been efforts to create compilation frameworks where templates for frequently occurring operations or operation clusters are extracted and mapped onto specialized cores.
ACM Transactions on Design Automation of Electronic Systems (January) by M. Gasteier, S. Liao, X. Song on the crossing distribution problem, J.-Y. Jou on two-level logic minimization for low power, F. Vahid on procedure cloning, Q. Wang, G. Yeap on power reduction and power delay trade-offs, others M. Glesner